The present invention relates to a technique for facilitation of a test and a debug on a semiconductor device. Further, it relates to a technique useful in application to a semiconductor device, e.g. an LC driver.
Examples of the literature covering a technique for facilitation of a test and a debug on a semiconductor device include Japanese Unexamined Published Patent Application No. JP-A-2003-315423, which discloses a liquid crystal controller arranged to input/output internal debug information from/to JTAG (Joint European Test Action Group). Further, in JP-A-2007-148754, there is a description concerning a technique for debug facilitation by which a boundary scan is executed according to initial settings on a TAP (Test Access Port) controller, and desired internal information pieces from CPU or another processing circuit are output through a debug terminal.
Prior to the invention, the inventor was examined on the patent documents: JP-A-2003-315423; and JP-A-2007-148754.